1. Field of Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a flash memory device.
2. Description of Related Art
An electrically erasable programmable read-only memory (E2PROM) is the memory device most often used in computers and electronic products because under the normal circumstances, the stored programs and information are retained and not erased. Erasure of the stored programs and information is achieved by subjecting the memory under an ultraviolet light for a period of time. The old programs and information are erased and new programs and information are stored. Moreover, the erasure of programs and information in an E2PROM is bit by bit. The stored information in an E2PROM is retained even when the power is interrupted. Additionally, the program function, the reading function and the erasure function can conduct for multiple times. Recently, a flash E2PROM is developed, wherein the erasure of information is block by block. The erasure function is therefore very fast and is normally accomplished in 1 to 2 seconds, which is faster than the normal E2PROM. The flash E2PROM is more time efficient and the manufacturing cost is also lower.
The fabrication of a flash memory device is normally combined with the fabrication of the peripheral circuit to simply the manufacturing process and to reduce the processing time. FIGS. 1A through 1D are schematic, cross-sectional views, illustrating the successive steps of fabricating a flash memory device according to the prior art, which is a concurrent fabrication of a flash memory device and a peripheral circuit.
FIGS. 1A through 1D are schematic, cross-sectional views, illustrating the successive steps of fabricating a flash memory device according to the prior art.
As shown in FIG. 1A, a first oxide layer 106 is formed on a substrate 100, which is already divided into a memory cell region 102 and a peripheral circuit region 104. A first conductive layer 108 is formed on the first oxide layer 106 in both the memory cell region 102 and in the peripheral circuit region 104. The first conductive layer 108 in the memory cell region 102 is then defined to form a plurality of floating gates 108a. A silicon oxide 110-silicon nitride 112-silicon oxide 114 (ONO) layer 116 is further formed on the substrate 100 in both the memory cell region 102 and the peripheral circuit region 104.
Referring to FIG. 1B, the first conductive layer 108, the silicon oxide layers 110, 114 and the silicon nitride layer 112 in the peripheral circuit region 104 are removed to expose the first oxide layer 106. A photoresist layer 122 is then formed on the silicon oxide layer 114 in the memory cell region 102. Using the first oxide layer 106 in the peripheral circuit region 104 as a sacrificial oxide layer 106a, an ion implantation 118 is conducted on the substrate 100 to form a doped region 120 in the peripheral circuit region 104.
As shown in FIG. 1C, subsequent to the ion implantation 118, the sacrificial oxide layer 106a is removed. The photoresist layer 122 is also removed using oxygen (O2) plasma and a sulfuric acid (H2SO4) aqueous solution. While the photoresist layer 122 is being removed, the polymer 124 debris on the surface of the floating gates 108a is exposed, reducing the reliability of the device. Moreover, the native oxide 126 on the substrate 100 surface in the peripheral circuit region 104 also adversely affects the quality of the subsequently formed gate oxide layer. In order to mitigate the aforementioned problems occurring in the prior art, a hydrofluoric acid aqueous solution is used to remove the polymer 124 debris on the floating gates 108a and the native oxide 126 on the substrate 100 surface. However, after resolving the polymer debris 124 and the native oxide 126 problems, other problem arises as illustrated in FIG. 1D.
Referring to FIG. 1D, subsequent to the removal of the polymer 124 debris and the native oxide 126 with the hydrofluoric acid solution, the top oxide layer 114 of the ONO gate dielectric layer 116 is eroded by the hydrofluoric acid solution. The original oxide layer 114 thereby becomes a thinner oxide layer 114a, leading to electrical problems.